1. Field of the Invention
The present invention relates to a clock generation circuit and a semiconductor device provided therewith.
2. Description of the Related Art
In recent years, a semiconductor in which various circuits are integrated on the same insulating surface has been developed, and a phase-locked loop circuit (hereinafter, referred to as a PLL circuit) has been known as a circuit which generates a clock with an arbitrary frequency synchronized with a supplied signal (hereinafter, a clock generation circuit).
A PLL circuit is mounted with a variable frequency oscillator, and compares a phase of a supplied signal with that of a feedback signal which is an output of the oscillator. The PLL circuit performs negative feedback control so that the supplied signal and the feedback signal can maintain a fixed phase relationship between the signals. The time required for such a control operation is called lock time.
Lock time is generally determined by the time constant of a loop filter inside a PLL circuit. If the time constant is large (if the cutoff frequency is low), locking is performed slowly, whereas if the time constant is small (if the cutoff frequency is high), locking is performed quickly. If the lock time is short, the control operation can be performed in a short time after a signal is supplied; however, since the operation is adversely affected in the case where the supplied signal has noise, it is difficult to maintain a stable control operation. Notwithstanding the aforementioned circumstance, a PLL circuit which can reduce the lock time independently of variation in operating conditions of a circuit and manufacturing conditions is known (for example, refer to Patent Document 1: Japanese Patent Laid-Open No. 2001-251186).
However, as shown in FIG. 17, a conventional PLL circuit has a phase detector 1711, a loop filter 1712 (hereinafter, referred to as LF), a voltage-controlled oscillator 1713 (hereinafter, also referred to as VCO), and a frequency divider 1714, which compares a phase of a supplied signal with that of a feedback signal (corresponding to an INPUT in FIG. 17) with a variable frequency inputted in the PLL circuit. Then, the PLL circuit performs negative feedback control so that the supplied signal and the feedback signal can maintain a fixed phase relationship between the signals.
In FIG. 17, the phase detector 1711 detects a phase difference between a signal Fs which is inputted from outside and a signal Fo/N which is inputted from the frequency divider 1714. The loop filter 1712 generates a signal Vin by removing alternating current components from a signal supplied from the phase detector 1711. The voltage-controlled oscillator 1713 outputs a signal Fo based on the signal Vin inputted from the loop filter 1712. The frequency divider 1714 converts the signal Fo inputted from the voltage-controlled oscillator 1713 into 1/N (frequency division by N), and outputs a signal Fo/N.
In this case, a stable and synchronized clock is generated because the PLL circuit compares a phase of a received signal with a signal Fs with a variable frequency from outside in a case where the signal Fs is received. However, in a case where the signal Fs with a variable frequency from outside is not received, the PLL circuit is necessary to maintain free running oscillation by a clock outputted from the PLL circuit itself.
Thus, free running oscillation becomes unstable when noise such as variation or the like in a power source is contaminated, and accordingly, a fixed and stable clock cannot be generated. Therefore, in a case where a stable power source from outside is not supplied, a frequency of a clock is varied during transmission after reception, which leads to malfunction of communication.
FIG. 18 shows an example in which a conventional PLL circuit generates a clock in synchronization with a received signal. In this example, the phase detector 1711 in FIG. 17 is a circuit which operates exclusive OR, for example, an exclusive OR circuit (hereinafter, a XOR circuit) shown in FIG. 18A. In FIG. 18B, data denotes a received signal, dclock (divide clock) denotes an output of the frequency divider 1714, which is a signal inputted to the phase detector by being fed back, and clock denotes an output of a VCO 1713. As shown in FIG. 18B, in a case where there is no input in a received signal data or a fixed state (H level or L level) maintain for a long time, the PLL circuit does not perform negative feedback control and performs free running oscillation. Accordingly, the problem occurs that clock is stopped when an output of the PLL circuit becomes unstable due to noise or the like of a power source.